Re: TI-H: TI Modem
[Prev][Next][Index][Thread]
Re: TI-H: TI Modem
Grant Stockly wrote:
> Now, since your doing bus access...we can generate a little 10MHz (1/3 of
> clock) refresh clock for some DRAM and have the ethernet card transfer to
> the DRAM, then the calc read it from the DRAM.
So you ARE doing a bus mastering thingie...
>
> >Did you transfer 8 megaBYTES or 8 megaBITS? I am afraid I am just a bit
> >skeptical... I don't see how you can transfer 8 Megabytes using a 2.5MHz
> >bus.
>
> With the ethernet card running 10MHz slower than the calc, there is a
> 3.75MHz bus clock (8 clock cycles per instruction) and a transfer rate of
> 7.5MByte/s
3.75 * 8 is 30 MHz. That's the card's speed? How is that 10MHz slower than the
calc?. 10 MHz slower than the calc would be stopped. I'm missing something.
>
> So, it can be done at 10MB to the memory, and 7.5Mbyte to the calc, 7.5/2
> if you want to do something with it.
Not exactly... close, but there is still an instruction fetch in there.
A normally clocked TI92 has a 2.5MHz bus, that's 4 clock cycles per bus cycle.
The move instruction is 2 bytes, which will take 1 bus cycle to fetch. Two bytes
are read in taking another bus cycle, then they are written to the other
location. That takes another bus cycle. That is three bus cycles per move
instruction. 5MByte bus bandwidth (bus speed of 2.5MHz, that's 10MHz/4, times 2
byte bus) at 3 bus cycles per instruction is 1.7 MByte maximum copy speed using a
10MHz 68000.
If the card has a 3.75 MHz bus that would be 7.5 MB to the DRAM and then 1.7 MB to
the calc.
Where did the 10MB per second come from? That would need a 5MHz bus speed
assuming that a processor is not doing the tansferring to the DRAM, or it would
need a 10MHz bus speed because of the instruction fetch..
--
-Calan
Chris Lambert
clambert@ieee.org
Member of Geneva College Student Branch IEEE
Head of Marvin Robotic Development Team
URL: www.geocities.com/SiliconValley/Peaks/6869
Follow-Ups:
References: