Re: TI-H: Another EIII choice...


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Re: TI-H: Another EIII choice...




That sounds great.  A 4.3GB HD would be a little much I think.  A keyboard
wouldn't be too hard as it's a serial(right?) device.
                                                         Jeff Rapp
                                                         jrapp@geocities.com
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     -  TI-Hardware Stuff
-----Original Message-----
From: Grant Stockly <gussie@alaska.net>
To: ti-hardware@lists.ticalc.org <ti-hardware@lists.ticalc.org>
Date: Saturday, April 04, 1998 4:58 PM
Subject: TI-H: Another EIII choice...


>
>This is more like it!  Check it!  It will have a real-time clock!
keyboard!
>
>This thing basically lets your calc use all PC/AT parts...  everything
>except the momitor...  I decided that a 2.88MB disk drive was enough, and
>that a 4.3GB $250 hard drive was overkill...  :)
>
>SuperI/O III
>+Plug and Play Compatible Chip
>+Floppy Disk Controller
>+Keyboard Controller
>+Real-Time Clock
>+Two Fast UARTS
>+Infrared Support
>+IEEE 1284 Parallel Port
>
>This fully Plug and Play (PnP) compatible chip incorporates a Floppy Disk
>Controller (FDC), a Keyboard and mouse Controller (KBC), a Real-Time Clock
>(RTC), two fast full function UARTs, Infrared (IR) support, a full IEEE
>1284 parallel port, three general purpose chip select signals that can be
>programmed for game port control, and a separate configuration register set
>for each module. It also provides support for power management (including a
>WATCHDOG timer) and standard PC-AT address decoding for on-chip functions.
>
>The Infrared (IR) interface complies with the HP-SIR and SHARP-IR
>standards, and supports all four basic protocols for Consumer Remote
>Control circuitry (RC-5, RC-5 extended, RECS80 and NEC).
>
>100% compatibility with Plug and Play requirements specified in the "Plug
>and Play ISA
>
>Specification", ISA, EISA, and MicroChannel architectures
>
>A special Plug and Play (PnP) module that includes:
>        Flexible IRQs, DMAs and base addresses that meet the Plug and Play
>requirements specified by Microsoft in their 1995 hardware design guide for
>Windows and Plug and Play ISA Revision 1.0A
>        Plug and Play ISA mode (with isolation mechanism-Wait for Key
state)
>        Motherboard Plug and Play mode
>
>A Floppy Disk Controller (FDC) that provides:
>        A modifiable address that is referenced by a 16-bit programmable
>register
>        Software compatibility with the PC8477, which contains a superset
>of the floppy disk controller functions in the [micro]DP8473, the NEC
>[micro]DP765A and the N82077
>        13 IRQ channel options
>        Four 8-bit DMA channel options
>        16-byte FIFO
>        Burst and non-burst modes
>        A high-performance, internal, analog data separator that does not
>require any external filter components
>        Support for standard 5.25" and 13.5" floppy disk drives
>        Automatic media sense support
>        Perpendicular recording drive support
>        Three-mode Floppy Disk Drive (FDD) support
>        Full support for the IBM Tape Drive Register (TDR) implementation
>of AT and PS/2 drive types
>
>A Keyboard and mouse Controller (KBC) with:
>        A modifiable address that is referenced by a 16-bit programmable
>register, reported as a fixed address in resource data
>        13 IRQ options for the keyboard controller
>        13 IRQ options for the mouse controller
>        An 8-bit microcontroller
>
>Software compatibility with the 8042AH and PC87911 microcontrollers
>        2 KB of custom-designed program ROM
>        256 bytes of RAM for data
>        Five programmable dedicated open drain I/O lines for keyboard
>controller applications
>        Asynchronous access to two data registers and one status register
>during normal operation
>        Support for both interrupt and polling
>        93 instructions
>        An 8-bit timer/counter
>        Support for binary and BCD arithmetic
>        Operation at 8 MHz, 12 MHz or 16 MHz (programmable option)
>        Customizability using the PC87323VUL, which includes a RAM-based
>KBC, as a development platform for keyboard controller code for the
>PC87307VUL
>
>A Real-Time Clock (RTC) that has:
>        A modifiable address that is referenced by a 16-bit programmable
>register
>        13 IRQ options, with programmable polarity
>        DS1287, MC146818 and PC87911 compatibility
>        242 bytes of battery backed up CMOS RAM in two bands
>        Selective lock mechanism for the RTC RAM
>        Battery backed up century calendar in days, days of the week,
>months and years, with automatic leap-year adjustment
>        Battery backed-up time of day in seconds, minutes and hours that
>allows a 12 or 24 hour format and adjustments for daylight savings time
>        BCD or binary format for time keeping
>
>
>                Power turned on when:
>                The RTC reaches a pre-determined date and time
>                A high to low transition occurs on the RI# input signals of
>the UARTs
>                A ring pulse or pulse train is detected on the RING# input
>signal
>                A SWITCH input signal indicates a Switch On event
>                Powered turned off when:
>                A SWITCH input signal indicates a Switch Off event
>                A Fail-safe event occurs (power-save mode detected but the
>system is hung up)
>                Software turns power off
>
>
>Two UARTs that provide:
>        Software compatibility with the 16550A and the 16450
>        A modifiable address that is referenced by a 16-bit programmable
>register
>        13 IRQ channel options
>        Shadow register support for write-only bits
>        Four 8-bit DMA options for the UART with Slow Infrared support
(USI)
>        An enhanced UART and Infrared (IR) interface on the USI that
supports:
>                UART data rates up to 1.5 Mbaud
>                HP-SIR
>                ASK-IR option of SHARP-IR
>                DASK-IR option of SHARP-IR
>                Consumer Remote Control Circuitry
>                A Plug and Play compatible external transceiver
>
>A bidirectional parallel port that includes:
>        A modifiable address that is referenced by a 16-bit programmable
>register
>        Software or hardware control
>        13 IRQ channel options
>        Four 8-bit DMA channel options
>        Demand mode DMA support
>        An Enhanced Parallel Port (EPP) that is compatible with the new
>version EPP 1.9, and is IEEE1284 compliant
>        An Enhanced Parallel Port (EPP) that also supports version EPP 1.7
>of the Xircom specification
>        Support for an Enhanced Parallel Port (EPP) as mode 4 of the
>Extended Capabilities Port (ECP)
>        An Extended Capabilities Port (ECP) that is IEEE 1284 compliant,
>including level 2
>        Selection of internal pull-up or pull-down resistor for Paper End
>(PE) pin
>        Reduction of PCI bus utilization by supporting a demand DMA mode
>mechanism and a DMA fairness mechanism
>        A protection circuit that prevents damage to the parallel port when
>a printer connected to it powers up or is operated at high voltages
>        Output buffers that can sink and source 14 mA
>        Three general purpose pins for three separate programmable chip
>select signals, as follows:
>
>
>Can be programmed for game port control
>
>
>16 single-bit General Purpose I/O ports (GPIO):
>        Modifiable addresses that are referenced by a 16-bit programmable
>register
>        Programmable direction for each signal (input or output) with
>configuration lock
>        Programmable drive type for each output pin (open-drain or
>push-pull) with configuration lock
>        Programmable option for internal pull-up resistor on each input pin
>with configuration lock
>        A back-drive protection circuit
>        An X-bus data buffer that connects the 8-bit X data bus to the ISA
>data bus
>
>Clock source options:
>        Source is a 32.768 kHz crystal-an internal frequency multiplier
>generates all the required internal frequencies
>        Source may be either a 48 MHz or 24 MHz clock input signal
>        Non-Volatile Memory (NVM) support via the Chip Select 0 (CS0#)
>signal that is powered by the VCCH
>        Enhanced Power Management (PM), including:
>
>                Special configuration registers for power down
>                WATCHDOG timer for power-saving strategies
>                Reduced current leakage from pins
>                Low power CMOS technology
>                Ability to shut off clocks to all modules
>
>
>