Re: LZ: TI 85 Memory Expander


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Re: LZ: TI 85 Memory Expander



On Wed, 11 Sep 1996 17:14:36 -0400 (EDT), you wrote:
>On Wed, 11 Sep 1996, Mel Tsai wrote:
>
>> I thought about this, but I figured it would be easier to do it the
>> way the TI-85 does it.  When you send a file to the expander, you send
>> a checksum byte to it (and then read it back to make sure there were
>> no errors in the checksum byte).  Then, when you want to reload the
>> file back to the TI-85, compare the checksum of the file with the
>> checksum byte, and if there was a difference you should read it again.
>> Of course, the file itself may have been corrupted during
>> transmission, so the parity checker may be necessary!  Anyone have any
>> suggestions to do a hardware parity check?
>>=20
>
>
>> >Now that I think about it, a toggle flip-flop might do the
>> >trick. =20
>> >
>>=20
>> What exactly do you mean by this?
>
>This is what I was thinking for a parity check in hardware.
>
>Since we might be checking theparity of 15+ bits (I am not sure exactly =
of
>the number of bits.  I would check the docs, but they are at home and I =
am
>at school) and the fact that the data is coming in serially, I figure a
>T-F/F would be the easist way of checking even/odd parity of the =
incoming
>bit stream in hardware. =20
>
>I would connect the T-F/F's clock to the clock (of course), and the =
input
>to the current incoming bit.
>
>Before any data is received, clear the F/F
>
>Then if the bit it high, toggle the F/F, if the bit is low, don't toggle
>it.  If the data was odd parity, then the F/F would be high at the end =
of
>the bit stream and if the parity was even, the F/F would be low.
>
>Basically a T-F/F's equation is:
>
>Q(T+1) =3D TQ' + T'Q
>
>I am not sure if this would be a "correct" way to do this, but from what=
 I
>see, it should work.  Since we are talking about low clock speeds,
>propigation times shouldn't be a problem.
>
>There should be IC's with T-F/F's.  You could also do it with And/NOR
>gates.  The circuit that I have in my digial logic book has 2-Three =
input
>AND's and 2-2Input NOR gates.  If you need the block diagram, ask me to
>post it.
>
>Anyone else have a suggestion?
>


Now I see what you mean.  Unfortunately, I see no easy way to send the
parity bit BACK to TI-85 without a few major modifications.  What you
said is definitely possible, however, and I'll think about it.  Maybe
sending the parity bit after the 32'nd cycle could be incorporated
(read the doc's if you don't know what I'm talking about...), but it
could take some finessing.


Yet another (and easy) option would be to actually read back every
byte you write to the memory (and if you are reading memory, read each
byte twice).  This will cut the data rate in half but it will
virtually eliminate all sources of error.


One potential problem that I see (that I haven't mentioned in the
documentation) is that if the serial CLOCK count, for some reason,
gets out of order, there is no way for the TI-85 to know and you could
end up writing false data everywhere before you know what hit you!
I'll have to come up with some sort of auto-hardware reset for the
expander so that can't happen.


-Mel


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