Re: A92: The trap funtion
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Re: A92: The trap funtion
In a message dated 3/31/98 12:22:23 PM Eastern Standard Time,
wshaver@shs.sps.lane.edu writes:
> Subj: Re: A92: The trap funtion
> Date: 3/31/98 12:22:23 PM Eastern Standard Time
> From: wshaver@shs.sps.lane.edu (Will Shaver)
> Sender: owner-assembly-92@lists.ticalc.org
> Reply-to: <A HREF="mailto:assembly-92@lists.ticalc.org">
assembly-92@lists.ticalc.org</A>
> To: assembly-92@lists.ticalc.org
>
>
> Ok, then what is an interrupt mask? And what is an SR? I know that an SP is
> the stack pointer, but havn't heard of an SR...
>
SR is the status register. It is composed of 2 bytes, or one word. The lower
byte,
aka the CCR, tells of the condition codes. Say you use "CMP #5,d0" and d0 is
#5. If it's five, the zero bit is turned on. WHy? Because cmp is like an
imaginary
subtraction. So 5-5=0. 0 turns on the zero bit of the CCR.
Okey, then we come to the upper byte of the SR, which is for supervisor
access.
[Read Chapter 6 in M68000 manual]: You can use it when you are in supervisor
mode. Supervisor mode is activated during: (a) forced exceptions [such as
traps]
, (b) interrupts [such as interrupt 1, which is an outboard timer, (I think)
and the
keyboard gives off interrupts too. Anything that's outside the processor gives
an
interrupt] (c) software errors [such as odd addresses. Illegal instructions,
this
will lead to the vectore assigned]
With all this mind, the upper byte of the SR contains the bits for supervisor
mode,
trace mode and the interrupt mask [say, you want to ignore the timer, you set
mask
to 2, so then, when the timer asks for a interrupt request, the processor
ignores it]
--Dennis Ng
NeoOS Team