[TI-H] Re: TI-89 HW2 overclocking


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[TI-H] Re: TI-89 HW2 overclocking



Now we just need to see the capacitance needed.

rabidcow@juno.com wrote:

>On Mon, 24 Feb 2003 16:54:44 -0500 "B.A. Baracus"
><babaracus@bellsouth.net> writes:
>  
>
>>I don't see anything called Chip Select, however, under Write Cycle, 
>>I see the following:
>>
>>Write Cycle Time                        min 85ns
>>Write Pulse Width                        min 60ns
>>Chip Enable to End of Write        min 75ns
>>
>>Is one of these the relevant value that is being exceeded by the 
>>calculator
>>that is preventing overclocking beyond 15~20MHz?
>>    
>>
>
>Now, I'm not 100% sure, but this seems to say that the fastest you can
>write is once every 85ns (that is, one write cycle takes 85ns, after
>which you can begin another) and you need to have the chip enable and all
>the proper signals stable for at least 60ns.  The timing diagrams seem to
>agree, but again I'm not sure.
>
>It looks like (dunno, 68k ain't my thing, I'm going by figure 4-2 in the
>68k user's manual), if the data strobe is used as chip enable, for a read
>it is enabled for 2 processor clocks, while for write it's only 1. 
>(although with a lower reliability it could be a little longer because of
>rise/fall time and because it'll go a little outside of its rating)
>
>This would mean that the processor clock period needs to be at least
>about 60ns for writes to work (min write pulse width), even if it only
>does a r/w operation at most once every 4 clocks (which would limit the
>proc. clock period to 85ns/4 = 22ns)
>
>60ns min processor clock period = 60 * 10^-9 s
>1/(60 * 10^9 s) = 16.7 * 10^6 1/s = 16.7 MHz max clock frequency
>
>My apologies is this is entirely wrong and misleading, it's been a while
>since I've done anything with electronics...
>
>-rabidcow
>
>
>   
>
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