[TI-H] Re: TI Networking.

To: ti-hardware@lists.ticalc.org
Subject: [TI-H] Re: TI Networking.
From: rabidcow@juno.com
Date: Wed, 2 May 2001 15:10:29 -0700
Reply-To: ti-hardware@lists.ticalc.org

Hence the quotes.
I'm not talking processor clocks, I'm talking link transitions clocks
(which don't have to technically exist), the rate at which line
transitions take place.

You can't guarantee that transmit and sample clocks are equal, but you
can guarantee that the sample rate isn't more than (eg) twice the
transmit rate.  If you couldn't syncronize at all then you'd be missing
bits like crazy.

TI's protocol is amazingly flexible, it'll work with radically different
sample/transmit clocks, but it's extremely inefficient if you don't need
that.

-josh

On Wed, 2 May 2001 16:51:06 -0500 "David Knaack" <dknaack@genetech.net>
writes:
> 
> From: <rabidcow@juno.com>
> > I think I would indicate a packet end by no line transitions for 2 
> or 3
> > "clocks"
> 
> What happens when an overclocked calc tries to talk to a 
> stock calc with low batteries?
> 
> Allowing for timeouts is good, but trying to use timing
> to handle transmissions in devices without any kind of
> reliable timing is probably a bad idea.  Thats probably
> one of the big reasons TI chose this hardware protocol
> for the calcs, the line speed is as fast as the slowest
> calc.
> 
> DK
> 
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Follow-Ups:

[TI-H] Re: TI Networking.

From: "David Knaack" <dknaack@rdtech.com>