Re: TI-H: High density SRAMs (4Mbit!!!)

To: ti-hardware@lists.ticalc.org
Subject: Re: TI-H: High density SRAMs (4Mbit!!!)
From: tsaimelv@pilot.msu.edu (Mel Tsai)
Date: Wed, 15 Jul 1998 03:36:34 GMT
Delivered-To: ti-hardware-outgoing@towerguard.unix.edu.sollentuna.se
In-Reply-To: <35ABF75A.72F980E1@geocities.com>
References: <35ABF75A.72F980E1@geocities.com>
Reply-To: ti-hardware@lists.ticalc.org


>Okay, these will be a pain to interface, but what do I care?  They're
>512 Kilobytes of Static RAM, and free samples at
>http://www.marshall.com/dynamic/html/mfrs/cyp/campaign/cyp3751.htm
>They do EAT power, though... 200mA or so.

This is only at the minimum cycle time, e.g. one chip access per 20ns.
Power consumption is directly proportional to how often you access the
chip.  If you access the chip say only 1 million times per second,
which is far less than what the chip is capable of, the power will
probably be under 10 mA if you keep the inputs at CMOS levels, e.g.
logic '1's are greater than 4.5 or 4.8 volts and logic '0' is under
0.2 volts.

Gotta love static HCMOS technology.

-Mel

References:

TI-H: High density SRAMs (4Mbit!!!)

From: Christopher Kalos <raptorone@geocities.com>

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