Re: A89: TSR on TI89 HW2
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Re: A89: TSR on TI89 HW2
On Mon, Jan 15, 2001, Jeff Flanigan wrote:
>
> Could someone give me a technical explanation of why
> stable TSRs are not possible on a TI89 HW2? Thank
> you!
The RAM is divided into 64 pages of 4Kb, and each page has an "execution
forbidden" bit. Every time the CPU performs an instruction fetch from RAM,
the corresponding bit is tested. If the bit is set, the calculator
instantly crashes.
By default, all pages are protected (except the page at $005000-$005FFF
because the OS sometimes copies code that cannot be executed in flash ROM to
this area). When an asm program is started, the OS temporarily deprotectes
the 4K pages that it occupies and JSR's to the first instruction. When the
program returns, the memory is protected again (maybe, I'm not sure, but it
doesn't matter).
A TSR would require a certain page to be deprotected all the time, which is
very hard to achieve without a workaround like HW2Patch.
The OS also imposes a limit on the program size (this limit is enforced by
the software only though) and the "launch" programs that must be used to run
large programs work by the fact that even though RAM is protected, the RAM
"shadow" at $040000-$07FFFF is not. They find the start address of the
program, add $040000, apply relocs and then jumps to the new address. (Ok,
that's not the whole story. The "shadow" RAM *is* protected, iff the last
RAM page (at $03C000-$03FFFF) is. This must be taken care of first.)
There's another protection feature that disallows instruction fetches from
archive memory. This protection is updated dynamically as the archive
memory grows.
HW1 calcs don't have the RAM protection, but they have a fixed archive
memory protection. This is why HW1 is limited to 384Kb of archive memory
unless you patch the OS.
--
Johan Eilert
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