Re: A89: timings and osc [was: TIGCCLIB 2.0 released!]


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Re: A89: timings and osc [was: TIGCCLIB 2.0 released!]




On Sat, May 27, 2000 at 17:06:25 -0400, Scott Noveck wrote:
> 
> Motorola 68k User's Manual, Section 7.7, Table 7.10 says that DBcc is 18
> cycles for false, 20 true (not the 10/14 you have above?) and I was only
> counting the difference between the rolled and unrolled loop (or the time
> taken just for the dbra command).  So I used 79 loops taken, 1 loop
> untaken, or 79*18 + 20 = 1,442.  Did I misinterpret something in the
> booklet?

My 68k UM (ninth edition), section 8.8, table 8.9 says 10/14/12 for branch
taken/counter expired/cc true on a 68000. Then I look at the 68008 timings
(chapter 7) and *they* match your figures! (The poor 68008 has an 8 bit data
bus and obviously needs *a lot* more cycles to fetch the word-sized
instructions...)

Unrolling the loop does virtually nothing (1%) when the actual copy eats all
the cycles. Perhaps only copying the visible part of the screen can speed up
things? Almost HALF the data that is copied ends up being invisible!

> > Use a stopwatch and measure the (exact) time it takes for the calc to APD.
> 
> Turned on, started timer, and I'm leaving it idle next to me now - we're
> expecting circa 300 seconds, correct?  If it makes a difference, I believe
> my batteries are running low but there's no indication yet (I left it
> running overnight in the middle of a prog that had disabled auto-int 1 =)

Yes, we're expecting something near 300 seconds, and if you haven't been
running anything that reprograms the timer, we'll actually get approx 300
seconds! The timer is originally programmed at another speed on HW2 calcs,
but the games/kernel/whatever reprogram it to the HW1 value...

> And the total is:  7:45.21, or approximately 465 seconds.  If we can safely
> assume that battery level is a factor, I'd guess that HW2 is only
> oscillating at 2/3 the speed - any idea why?

Then I finally know for sure; the speed of the HW2 osc IS in fact almost
exactly 2/3 of the HW1 osc! *updating my hw info doc*

Battery level does not matter. The oscillators are always running at the
same speed (unless the batteries are DEAD of course! :) )
(One visual evidence of this is that the LCD doesn't gradually lose
contrast, as on the older calcs.)

On HW1, the programmable timer is set (by the OS) to generate an interrupt
after 79 increments (approx 20 Hz). On HW2, this value is 53. And it's not a
big surprise that 53/79 =~ 2/3. I assume that TI wanted it to be approx 20
Hz on both HW1 and HW2.

I calculate the osc speeds by knowing that the APD timer starts at 6000
every time a key is pressed and that APD occurs when the timer reaches zero.
I also know that the oscillator "oscillates" 2^9*79 times between each APD
timer count. Thus I can measure how many seconds it takes to do 6000*2^9*79
oscillations, and find the oscillator speed.

Now, back to reality. All this means that HW1 screen refresh is 94 Hz
(effectively 31 Hz in four-level grayscale), but HW2 screen refresh is only
64 Hz (a mere 21 Hz in grayscale!). The maximum refresh rate possible (full
screen) on a HW2 calc (TI89) is 80 Hz. If you can take unusable bars at the
top and bottom of the screen (like the black bars above and below a 16:9
movie on a 4:3 TV), it'd be possible to increase it to, say, 90 Hz.

Anyway, I shut up now. Thanks for the APD info! =)


/Johan



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