A86: TI86 RAM layout


[Prev][Next][Index][Thread]

A86: TI86 RAM layout




   This is an overview of the TI86 addressing design. 
   The RAM is accessed 'mostly' through 'absolute addressing'
   overlayed over the banked or paged RAM. A 24-bit address is 
   used.   

   I know this isn't much detail but I am still working on the statistics
   application. I do monitor this list and will try and answer 
   questions when I have time.

   Later,
   Pat

                 MEMORY RAM MAP
                 --------------


  0000h       -------------------------
  (ASIC)     |                         |
             |   ROM PAGE 0            |
             |                         |
  4000h      |-------------------------|
             |                         |
             |   SWAPPED ROM PAGE(1-F) |
             |                         |
  8000h      |------------------------ |
             |                         |
             |   SWAPPED RAM PAGE (1-7)|
             |                         |
  C000h      |-------------------------|
             |                         |
             |   STATIC RAM PAGE (0)   |
             |                         |
              -------------------------

                RAM PAGE 0 (16k)           ABS = ABSOLUTE ADDRESS
 0C000h  -------------------------
 (ABS)  |                         |    ABS             RAM PAGE    ASIC ADDR
        |  system memory          |    ----            --------    ---------
        |                         |    0C000-0FFFF        0        C000-FFFF
        |-------------------------|    10000-13FFF        1        8000-BFFF
        | INTER BANK RAM CACHE    |    14000-17FFF        2        8000-BFFF
        |-------------------------|    18000-1BFFF        3        8000-BFFF
        |  RESEVERED RAM FOR      |    1C000-1FFFF        4        8000-BFFF
        |  ASSEMBLY LANGUAGE      |    20000-23FFF        5        8000-BFFF
        |  PROGRAMMING ~ 10k      |    24000-27FFF        6        8000-BFFF
        |-------------------------|    28000-2BFFF        7        8000-BFFF
        |       ^                 |
        |       :                 |
        |  hardware stack         |               RAM PAGES 2 - 7 (96K)
 0FC00h |-------------------------|    14000  -------------------------
        |  display                |    (ABS) |   USER MEMORY           |
 0FFFFh  -------------------------           |        |                |
                                             |        v                |
              RAM PAGE 1 (16K)               |.........................|
10000    -------------------------  FPBASE   |   TEMP MEMORY           |
(ABS)   |  floating point stack   |          |        |                |
        |       :                 |          |        v                |
        |       v                 |          |.........................| ---
        | . . . . . . . . . . . . | *FPS     |         ^               | 1  |
        |                         |          |         |               | 6  |
        | FREE EXEC RAM           |          |   TEMPS SYM TABLE       | K  |
        | . . . . . . . . . . . . | *OPS     |.........................|    |
        |       ^                 |          |         ^               | M  |
        |       :                 |          |         |               | A  |
        |  operator stack         |          |   USER SYM TABLE        | X  |
13FFF    -------------------------  OPBASE    ------------------------- ----
(ABS)

  * TO ACCESS FPS LOAD PAGE 1 AND ADD 8000h TO 2 LSB'S OF ABS ADDRESS
  * TO ACCESS SYMTABLE LOAD PAGE 7 AND USE 2 LSB'S OF ABS ADDRESS


EX: after findsym  the registers B,D,E is the "absolute" address of 
    the data ptr for the var. And HL is the lower 2 bytes of "absolute" address
of the symbol table entry, the MSB is always '2' for symbol table entries.

    In order to access the data @ ABS address 'bde' system routines are
    used to convert ABS addresses to addresses that the 86 hardware sytem
    understands, in the range of 8000h-bfffh and also have the correct
     RAM page "swapped in". In other words on 16k of user ram can be available
    at any given time for the 86 system to access, that is why nearly all
    memory access are done using this "absolute addressing" so that worring
    about what ram page is loaded is not a problem. This will cause some
    slowness but the z80 only has a 64k address space. You can see that
    I divide that address space into 4 parts : 

                                              16k page 0 system rom
                                              16k for rom page swapping
                                              16k for static system ram 
                                              16k for ram page swapping