[A83] Re: im 2


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[A83] Re: im 2




> From: David Phillips <david@acz.org>
> 
> This is old news :)  People have been doing it on the 85 and 86 for a very
> long time.  On the 85, it's the only way to do an interrupt handler.

I know, but I brought up the issue again, because my routine really needs to be as fast as possible. Every tstate counts. So I thought, by splitting it up into several routines, which are randomly called, each routine could be faster than when I had to put them together and built in a counter.

> You bring up an interesting point regarding the lower bit being 0 to produce
> word aligned addresses.  Technically, it may be that the device generating
> the interrupt should always do this.

As far as I know now, the lower bit seems to be more 1 than 0. Also, when I use a _getcsc/halt loop in the main program, the lowest bit seems to be always 1, resulting in aligned addresses. Don't ask me why that is.

> Matt Johnson was confused by this very issue on the 86 Central interrupt
> section.  Because there is only two interrupting devices, the timer
> interrupt and the on interrupt, and neither of them generate a value, you
> must assume that it is random.
> As such, 257 different addresses can be generated.  This means that your
> interrupt table must be 257 bytes long.

So why didn't TI put in a decent interrupting device for us poor programmers?

--Tijl Coosemans
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