[TI-H] Re: TI-89 HW2 overclocking
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[TI-H] Re: TI-89 HW2 overclocking
On Tue, 25 Feb 2003 08:08:20 +0100, Olle Hedman <alh@home.se> wrote:
> Chip Select, Chip Enable, same thing different name. From the chips point
> of view it gets "enabled" from the cpus point of view it "selects" the
> chip (by enabling it)
> The lower value should be the relevant. Maybe in conjuction with the
> second. I'm not sure here though.
>
> about the 15MHz it is the highest Johan recommends for a stable calc.
> ~20MHz and it becomes unreliable.
> Maybe that answers your confusion.
Referring to rabidcow's post, "This would mean that the processor clock
period
needs to be at least about 60ns for writes to work (min write pulse width),
even if it only does a r/w operation at most once every 4 clocks," I seem
to
understand that the highest speed the CPU can be clocked to (to remain
within
specifications) is 1/(min write pulse width).
For the HW2 and its RAM, 1/(60ns) = 16.7MHz
For the HW1 and its RAM, 1/(55ns) = 18.2MHz
However, this datasheet lists write pulse width as 55ns and its "chip
select 1"
and "chip select 2" as 60ns, making the clock 16.7MHz.
(datasheet: http://www.it.lth.se/datablad/Memory/sram/srm20v100.pdf)
Now, for the crux of my inquiry:
Could the SRAM modules on the TI-89 HW2 be replaced with SRAMs from another
manufacturer that have identical voltage/pinout/memory width/size
characteristics,
but have faster access times?
One candidate I have found:
Cypress CY7C62128V-55, has 45ns "write pulse width", giving theoretical max
CPU
speed of 22.2MHz.
(datasheet: http://www.cypress.com/cfuploads/img/products/38-05061.pdf)
Anyone more knowledgeable than I is welcome to comment on the validity of
my
assumptions and conclusions.
--
B.A. Baracus
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