RE: TI-H: direct bus access

To: "'ti-hardware@lists.ticalc.org'" <ti-hardware@lists.ticalc.org>
Subject: RE: TI-H: direct bus access
From: Christopher Kalos <raptorone@stuytech.com>
Date: Tue, 20 Jan 1998 00:29:17 -0500
Reply-To: ti-hardware@lists.ticalc.org

EMS, the enhanced memory spec back in the XT days...
It used 64K pages to switch banks of extra RAM.  Reduce that to say, 16K or 8K pages, and you're set.  actually, address it by 16-bit values.  64K is available, and then implement a method of switching pages.  It's slow, but can allow you to have a lot more space, provided you can find a place to stash the RAM chips.
Christopher Kalos
raptorone@stuytech.com
Executive Director/Administrator
Virtual Technologies Developer's Group


----------
From: 	Christopher Lambert[SMTP:clambert@sparcy.geneva.edu]
Sent: 	Monday, January 19, 1998 9:56 PM
To: 	ti-hardware@lists.ticalc.org
Subject: 	TI-H: direct bus access



Would anyone care if I told you that I have achieved direct bus access to 
a TI 92?  This has enabeled me to create external memory-mapped I/O 
ports.  Is this a good thing or does anyone even care?

Chris Lambert
clambert@geneva.edu
calan@hotmail.com
URL: www.geocities.com/siliconvalley/peaks/6869

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