RE: TI-H: 68000


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RE: TI-H: 68000



The more addressing pins that the manufacture places on the chip, the easier it is
to integrate into larger systems. It lowers the external chip count because
address decoding is not needed.

As for using a 8 bit on a 16 bit bus, this is very common. You simply place two
together and you now have a 16 bit memory. It is also common on very large memory
arrays to place single bit chips in whatever rows are needed. For instance a 16
bit data line would have 16 chips of whatever capacity was needed. Less common are
arrays such as 2ea 4 bits + a single bit so that you have a total of 9 bits for parity
and other bazaar configuration. Up until seven years ago, nearly all memory arrays
where single bit in rows!

-----Original Message-----
From:	Christopher Lambert [SMTP:clambert@sparcy.geneva.edu]
Sent:	Sunday, September 28, 1997 9:07 PM
To:	ti-hardware@lists.ticalc.org
Subject:	Re: TI-H: 68000


I have the pinout of the RAM chip...  I just don't know why a 128K chip 
has 20 or so addressing pins.  And I don't understand how they are using 
an 8-bit memory chip with a 16-bit data bus.  If anyone knows any 
answers, please explain.

Chris Lambert
clambert@geneva.edu

On Mon, 29 Sep 1997, Matthew H. Fogle wrote:

> This 92 ram chip sounds like a 128k static ram chip with 32 pins. Its
> what HP used in the HP48 series. Is this possibly the chip? If so I have
> pinouts for you...
> 
> -=<Matt>=-
> 
> 
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