[A83] Re: Interrupt Vector


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[A83] Re: Interrupt Vector



Jeff Theusch writes:
> This means that the table only has to be 256 bytes, not 257, and that
> the interrupt vector can point to anywhere, not just to where the
> most and least significant bytes are the same.  This is contrary to
> many of the tutorials I have read about the TI-83.  Can anyone
> confirm or disprove this?

That's wrong.  Though, you're not the first person to make that mistake.
Matt Johnson thought that also when he wrote 86 Central way back when:

http://ti86.acz.org/interrupts.htm

``Jimmy Mardell claims you need a 257 byte table, but I believe he is wrong.
Let me elaborate - According to the IM 2 documentation by Zilog as I quote -
"The lower 8-bits of the pointer must be supplied by the interupting device.
Actually, only seven bits are required from the interrupting device as the
least significant bit must be zero. This us required since the pointer is
used to get two adjacent bytes to form a complete 16-bit service routine
starting address and the addresses must always start in even locations". OK,
so it will retrieve an even address. Suppose the vector table starts at
$8E00 and is filled with all $8F. The vector table starts at $8E00, and ends
at $8EFF. This is a total of 256 locations. But since it starts at an even
location, the 16-bit number retrieved from the vector table can only be (at
the most) $8EFE (which is even). Then a 16-bit address is formed where the
first byte would be $8EFE and the second at $8EFF. Notice this is only 256
bytes. What I believe Jimmy Mardell thought is that it could jump anywhere
in the table up to $8EFF, get the first byte from here, and get the next
byte at $8F00. This would be incorrect since the address must be even and
$8EFF is not an even number.

[Reply from Jimmy Mardell:]
I've read that, but he's wrong.  I've tried with a 256 table, and it crashed
immediately :) I don't know where he read that it must be an even number -
that's absolutely wrong.  I mean, _ANY_ number can be on the databus since
the interrupt isn't supported.  On CPU's that supports IM 2, the peripherals
which are connected to it mosy likely only "sends" (or whatever) even bytes,
but that's beside the point.''

--
David Phillips <david@acz.org>
http://david.acz.org/




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